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buck or boost, pwm controller for battery test solutions data sheet ADP1972 features input voltage range: 6 v to 60 v on - board 5 v low dropout regulator selective buck or boost mode excellent pwm linearity with high amplitude pwm sawtooth 4.0 v p - p fault input compatible with ad8450 comp input compatible with ad8450 adjustable frequency from 50 khz to 300 khz synchronization output or input with adjustable phase shift programmable maximum duty cycle maximum i nternal d uty cycle: 98% programmable soft start peak h iccup current limit protection input voltage uvlo protection tsd protection 16- lead tssop applications pwm battery test systems with re cycle capability including hybrid vehicle s, pcs , and camera batteries comp atible with ad8450 constant voltage (cv) and constant current (cc) monitor s general description the ADP1972 is a constant frequency, volta ge mode , pulse - width modulation ( pwm ) controller for buck or boost , dc - to - dc , asynchronous a pplications. the ADP1972 is designed for use in asynchronous battery testing applications with an externa l , high voltage field effect transistor ( fet ) , half brid g e driver , and an external control device, such as the ad8450 . the asynchronous device operates as a buck converter in battery charge mode and operates as a boost converter in recycle mode to re cycle energy to the input bus. the ADP1972 high voltage , vin supply pin can withstand a ma ximum operating voltage of 60 v and reduces the need fo r additional system supply voltages. the ADP1972 has integrated features such as precision enable , pin selective buck or boost mode operation, internal and external synchronization control with pro grammable phase shift, programmable maximum duty cycle, and programmable peak hiccup current limit . additional protection features include soft start to limit input inrush current during startup, input voltage undervoltage lockout ( uvlo ) , and thermal shutd own ( tsd ) . t he ADP1972 also has a comp pin to provide external control of the pwm operation and a fault pin that can be signaled to disable the dh and dl outputs if a fault condition occurs externa l ly to the ADP1972 . the ADP1972 is available in a 16 - lead tssop package. typical application circuit dh dl cl gnd 24v recylcing dc bus vin 24v en comp fault mode from central pc from analog ic ADP1972 vreg freq sync dmax scfg ss gnd sense hv mosfet driver battery 11884-001 figure 1 . rev. 0 document feedback information f urnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subj ect to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, nor wood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com free datasheet http://www..net/
ADP1972 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal operating ranges ......................................................... 5 esd caut ion .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 supply pins .................................................................................. 10 en/shutdown .............................................................................. 11 undervoltage lockout (uvlo) ............................................... 11 soft start ...................................................................................... 11 operating modes ........................................................................ 11 pwm drive signals .................................................................... 12 external comp control ........................................................... 12 current limit .............................................................................. 12 pwm frequency control .......................................................... 12 maximum duty cycle ............................................................... 13 external fault signaling ............................................................ 13 thermal shutdown (tsd) ........................................................ 13 applications information .............................................................. 14 buck or boost selection ............................................................. 14 selecting r s to set the current limit ....................................... 14 adjusting the operating frequency ........................................ 14 programm ing the maximum duty cycle ............................... 15 adjusting the soft start period ................................................. 16 pcb layout guidelines .................................................................. 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 1/ 14 revision 0: initial version rev. 0 | page 2 of 20 free datasheet http://www..net/
data sheet ADP1972 specifications vin = 24 v and the specifi cations are valid for t j = ?40 c to +125 c, unless otherwise specified. typical values are at t a = 25 c. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). table 1. parameter symbol test co nditions/comments min typ max unit input voltage ( vin ) v oltage range v in 6 60 v vin supply current i vin r freq = 100 k?, v ss = 0 v , sync floating 1.5 2.5 ma vin shutdown current i shdn v en = 0 v 15 70 a uvlo threshold rising v in rising 5.71 6 v uvlo threshold falling v in falling 5.1 5.34 v soft start (ss) ss pin current i ss v ss = 0 v 4 5 6 a ss threshold rising 0.52 0.65 v ss threshold falling 0.4 0.5 v pwm control freq frequency range f set 50 300 khz os cillator frequency f osc r freq = 100 k? 90 100 110 khz freq pin voltage v freq r freq = 100 k? 1.2 1.252 1.3 v sync maximum sync pin voltage 5.5 v sync pull - down resistor 0.5 1 1.5 m? sync output (internal frequency control) v scfg 4.5 3 v or scfg pin floating inte rnal sync range f set for sync output 50 300 khz sync output clock duty cycle v scfg = v vreg , r freq = 100 k? 40 50 60 % sync sink resistance r sync v scfg = 5 v, i sync = 10 ma 10 20 ? sync input (external frequency control) v scfg < 4. 2 5 v external sync range f s ync for sync input clock 50 300 khz sync threshold rising 1.2 1.5 v sync threshold falling 0.7 1.05 v r freq slave to master ratio for synchronization for example, r freq ( slave ) = 1.1 1 r freq ( master ) 1.11 scfg v scfg scfg high threshold rising 4.5 3 4.7 v scfg high threshold falling 4.25 4.51 v scfg low threshold rising 0.52 0.65 v scfg low threshold falling 0.4 0.5 v scfg current i iscfg r freq = 100 k? 9.5 11 12.5 a dmax maximum internal duty cycle v comp , v dmax , v ss , and v scfg = 5 v 97.37 % dmax setting current i dmax v dmax = 0 v, r freq = 100 k? 9.5 11 12.5 a dmax and scfg current matching 1 10 % comp maximum comp pin voltage v comp 5 v internal peak - to - peak ramp voltage v p - p 4 v comp maximum internal ramp voltage 4.5 v comp minimum internal ramp voltage internal oscillator is disabled 0.45 0.5 0.55 v dh and dl shutdown range 2 v comp comp not regulated 0.45 v maximum duty cycle range 2 v comp 4.4 5 v rev. 0 | page 3 of 20 free datasheet http://www..net/
ADP1972 data sheet parameter symbol test co nditions/comments min typ max unit precision enable logic (en) maximum en pin voltage 60 v en threshold rising 1.25 1.4 v en threshold falling 1.1 1.22 mv en pin current v en = 5v 0. 32 2 a mode logic maximum mode pin voltage 5.5 v mode threshold rising 1.20 1.5 v mode threshold falling 0.7 1.05 v current limit (cl) set current i cl v cl = 0 v 18 20 21 a buck internal reference v ref (buck) 250 300 350 mv boost internal reference v ref (boost) 450 500 550 mv hiccup detect time r freq = 100 k ? 4.4 5.2 6.1 ms hiccup off - time r freq = 100 k? 4.4 5.2 6.1 ms vreg ldo regulator output voltage v v reg v in = 6 v to 60 v 4.9 5 5.1 v guaranteed output current i out (max) v in = 6 v 5 ma line regulation v in = 6 v to 60 v 5 5.1 v load regulat ion v in = 6 v , i out = 0 ma to 5 ma 5 5.1 v fault maximum fault pin voltage 60 v fault threshold rising 1.2 1.5 v fault threshold falling 0.7 1.05 v fault pin current v fault = 5 v 0.49 2 a pwm drive logic signals (dh/dl) dl drive voltage v dl no load vreg v dh drive voltage v dh no load vreg v dl and dh sink resistance i dl = 10 ma 1.2 2.4 ? dl and dh source resistance i dl = 10 ma 1.4 2.6 ? dl and dh pull - down resistor 0.5 1 1.5 m? thermal shutdown (tsd) tsd threshold rising 150 c tsd threshold falling 135 c 1 the dmax and scfg c urrent m atching specification is calculated by taking the absolute value of the difference between the measured i scfg and i dmax currents, dividing them by the 11 a typical value, and multiplying this answer by 100. 100 a 11 (%) ? ? ? ? ? ? ? ? ? = dmax scfg i i t matching cfg curren dmax and s 2 see figure 11 for a graph of the duty cycle vs. the applied comp pin voltage. rev. 0 | page 4 of 20 free datasheet http://www..net/
data sheet ADP1972 absolute maximum rat ings table 2. parameter rating vin, en, fault to gnd ? 0.3 v to +61 v sync , comp , mode to gnd ? 0.3 v to +5.5 v dh, dl, ss, dmax, scfg, cl to gnd ? 0.3 v to vreg + 0.3 v gnd sense to gnd ? 0.3 v to +0.3 v operating ambient temperature range ? 40c to +85c junction temperature 12 5c storage temperature range ? 65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any othe r conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. absolute maximum ratings apply individually only, not in combination. thermal operating ra nges the ADP1972 can be damaged when the junction temperature limits are exceeded. the maximum operating junction temperature (t j max ) takes precedence over the maximum operating ambient temperature (t a max ). monitoring ambient temperature does not guarantee that the junction temperature (t j ) is within th e specified temperature limits. in applications with high power dissipation and poor printed circuit board ( pc b ) thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit when the junction temperature is wit hin specification limits. the junction temperature ( t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction to ambient thermal resistance of the package ( ja ). use the following equation to calculate the m aximum junction temperature (t j ) from the ambient temperature (t a ) and power dissipation (p d ): t j = t a + (p d ? ja ) (1) for additional information on thermal resistance, refer to application note an - 000, thermal characteristics of ic assembly . esd caution rev. 0 | page 5 of 20 free datasheet http://www..net/
ADP1972 data sheet pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ADP1972 top view (not to scale) dh vreg vin sync mode en dl fault gnd sense gnd scfg ss comp dmax freq cl 1 1884-002 figure 2 . pin configuration table 3 . pin function descriptions pin o. neonic description 1 dl logic drive low output for external low - side mosfet driver . 2 dh logic drive high output for external high -s ide mosfet driver . 3 vreg internal low d ropo ut (ldo) voltage regulator output and internal bias supply. a bypass c apacitance of 1 f or greater from this pin to ground is required . 4 vin high input voltage supply pin . bypass this pin with a 4.7 f capacitor to ground . 5 en logic enable input . drive en logic low to shut down the device . d rive en logic high to turn on the device . 6 mode mode select . drive mode logic low to place the device i n boost/recycle mode . drive mode l ogic high to place the device in buck/charge mode of operation . 7 sync synchronization pin. this pin is used as a n input and synchronized to an e xternal clock or used as an output clock to synchronize with other channels . 8 fault fault input pin. signaled by an overcurrent protection ( ocp ) or overvoltage protection ( ovp ) fault c ondition on the c ompanion asic , ad8450 . the ADP1972 is disabled until this pin i s logic high. 9 comp output error amplifier signal from the c ompanon asic , ad8450 . this pin is the error input to the ADP1972 and is compared internally to the linear ramp to produce the pwm signal. do not leave this pin floating. 10 ss soft start control pin. a ca pacitor connected from ss to ground brings the output up slowly during power - up and reduces the inrush current. 11 dmax maximum duty cycle input. connect an external resistor to ground to set the maximum duty cycle. if the 98% internal maximum duty cycle is sufficient for the application, tie this pin to vreg . if dmax is left floating, this pin is internally tied to vreg. 12 freq frequency set pin . connect an external resist or between this pin and ground to set t he frequency between 50 khz and 3 00 khz. 13 scfg synchronization configuration i nput. drive v scfg 4.53 v to configure s ync as an output clock signal. drive v scfg < 4. 2 5 v to configure sync as an input. connect a resistor to ground with 0. 6 5 v < v scfg < 4. 25 v to introduce a phase shift to the synchronized clock. drive v scfg 0.5 v to configure sync as an input with no phase shift s o that it synchronize s the device to an external clock source. if scfg is left floating, the sync pin is internally tied to vreg , and sync is configured as an output . 14 gnd power and analog ground pin . 15 gnd sense ground sense for the cur rent - limit setting resistor. 16 cl current - limit pro gramming pin. connect a current - limit sense resistor in series with the fet source to set the peak current limit. rev. 0 | page 6 of 20 free datasheet http://www..net/
data sheet ADP1972 typical performance characteristics v v in = v en = v fault = 24 v, v mod e = v cl = v ss = v comp = 0 v , t a = 25c , unless otherwise noted. 5.8 5.7 5.6 5.5 5.4 5.3 5.2 ?40 ?5 30 65 100 vin uvlo threshold (v) temperature (c) rising falling 1 1884-003 figure 3 . input voltage uvlo threshold vs. temperature , v fault = 0 v 30 0 5 10 15 20 25 6 60 51 42 33 24 15 shutdown current (a) input voltage (v) t a = ?40c t a = +25c t a = +125c 1 1884-004 figure 4 . sh utdown current vs. input voltage , v en = 0 v and v fa ult = 0 v 1.9 1.3 1.4 1.5 1.6 1.7 1.8 6 60 51 42 33 24 15 nonswitching quiescent current (ma) input voltage (v) t a = ?40c t a = +25c t a = +85c t a = +125c 1 1884-005 figure 5 . nonswitching quiescent current vs. input voltage ( sync = f loating ) 0.45 0.15 0.20 0.25 0.30 0.35 0.40 6 60 51 42 33 24 15 en pin current (a) en pin voltage (v) t a = ?40c t a = +25c t a = +125c 1 1884-007 figure 6 . en pin current vs. en pin voltage , v en = 5 v and v fault = 0 v 1.25 1.20 1.21 1.22 1.23 1.24 ?40 ?5 30 65 100 en pin threshold (v) temperature (c) rising falling 1 1884-008 figure 7 . en pin threshold vs. temperature , v fault = 0 v 5.00 4.88 4.90 4.92 4.94 4.96 4.98 ?40 120 80 40 0 ss pin current (a) temperature (c) v in = 6v v in = 24v v in = 60v 1 1884-009 figure 8 . ss pin current vs. temperature rev. 0 | page 7 of 20 free datasheet http://www..net/
ADP1972 data sheet 97.8 97.2 97.3 97.4 97.5 97.6 97.7 6 60 51 42 33 24 15 maximum internal duty cycle (%) input voltage (v) t a = ?40c t a = +25c t a = +125c 1 1884-010 figure 9 . maximum internal duty cycle vs. input voltage , r freq = 100 k?, v comp = 5 v , and no l oad on dl, dh, or dmax 450 0 50 100 150 200 250 300 400 350 0 20 40 60 80 100 r dmax (k?) duty cycle (%) t a = ?40c t a = +25c t a = +125c 1 1884-0 1 1 figure 10 . r dmax vs. duty cycle , r freq = 100 k, v comp = 5 v, and no l oad on dl or dh 100 80 60 40 20 0 0.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 duty cycle (%) v comp (v) t a = ?40c t a = +25c t a = +125c 1 1884-018 figure 11 . duty cycle vs. v comp , r freq = 100 k , and no l oad on dl, dh, or dmax 210 30 50 70 90 110 130 150 170 190 50 100 150 200 250 300 r freq (master) (k) f set (khz) 1 1884-015 figure 12 . r freq (master) vs. switching frequency (f set ) 5.020 4.990 4.995 5.000 5.005 5.010 5.015 6 60 51 42 33 24 15 vreg (v) input voltage (v) t a = ?40c t a = +25c t a = +85c t a = +125c 1 1884-016 figure 13 . vreg vs. input voltage , no l oad 5.020 4.980 4.985 4.990 4.995 5.000 5.005 5.010 5.015 0 5 4 3 2 1 vreg (v) load current (ma) t a = ?40c t a = +25c t a = +85c t a = +125c 1 1884-017 figure 14 . vreg vs. load current rev. 0 | page 8 of 20 free datasheet http://www..net/
data sheet ADP1972 1 1884-014 ch1 10.0v ch2 5.0v 5.0gs/s ch3 5.0v ch4 5.0v 10m points 100s ch1 7.00v 1 2 3 4 t 14.42% t en dl vreg sync v in = 24v v comp = 2.5v no c ss figure 15 . startup rev. 0 | page 9 of 20 free datasheet http://www..net/
ADP1972 data sheet theory of o peration freq sync vin v bg = 1.252v sync detect 5a vreg comp ss fault r s gnd sense en ADP1972 vreg ad8450 ad8450 dmax scfg gnd tsd vreg uvlo band gap mode vreg dh dl drive logic oscillator config detect cl vreg external driver 5v 15v 24v vout 500mv 300mv mode select 4v i freq i ss i cl 20a mode select pgnd agnd 1m 1m 1 m? i freq i freq r cl 20k c in 4.7f c vreg 1f c out l m1 m2 r freq c ss r dmax c dmax vreg = 5v vreg 8.5m? 1 1884-020 figure 16 . block diagram the ADP1972 is a cons tant frequency, voltage mode , pwm co ntroller for buck or boo s t, dc - to - dc , asynchronous applicati ons with an external , high voltage fet , half brid g e driver , and an external error signal generating device, such as the ad8450 . the ADP1972 has a high input voltage range , multiple externally programmed control pins, and integrated safety features. supply pins the ADP1972 has two voltage supply pins, vin and vreg. the vin pin operates from an external supply that range s from 6 v to 60 v and is the su ppl y voltage for the internal ldo regulator of the ADP1972 . bypass the vin pin to ground with a 4.7 f or greater ceramic capacitor. th e vreg pin is the output of the internal ldo regulator. the internal ldo regulator generates the 5 v (typical) rail that is used internally to bias the control circuitry and can be used externally as a pull - up voltage for the mode, sync, dmax, and fault pi ns. bypass the vreg pin to ground with a 1 f ceramic capacitor. when operating with an input voltage above 50 v, additional input filtering is necessary. fig ure 17 shows the recommended filter configuration . vin supply > 50v 4.7f c ADP1972 r 1 1884-021 fig ure 17 . recommended filter configuration for input voltages greater than 50 v rev. 0 | page 10 of 20 free datasheet http://www..net/
data sheet ADP1972 e n / s hutdown the en input turns the ADP1972 on or off. the en pin of the ADP1972 can operate from voltages up to 60 v and is designed with stable 20 % thresholds for precision enable control. when the en voltage is less than 1.2 2 v (typical) , the ADP1972 shut s down, driving both dl and dh low. when the ADP1972 is shut down , the vin supply current is 15 a (typical). when the en voltage is greater than 1.25 v (typical) , the ADP1972 is enabled. the device can be disabled via the en pin , a fault condition indicated by a tsd event, a uvlo condition, or an external fault condition signaled via the fault pin. undervoltage lockout (u vlo) there is i nternal uvlo for the vin pin. when vin rises, the uvlo does not allow the ADP1972 to turn on unless vin is greater than 5. 71 v (typical) . when vin falls , the uvlo disable s the device w hen v in drops below 5. 34 v (typical) . th e uvlo prevents potentially erratic operation of the application at low input voltages that may damage the ADP1972 and the external circuitry. the uvlo levels have ~3 7 0 mv of hysteresis to ensure glitch free startup. soft start the ADP1972 is equipped with a programmable soft start that prevents output voltage overshoot during startup. when the ADP1972 is enabled with the en pin, the vreg vo ltage begins rising to 5 v. when vreg reaches 90% of its 5 v (typical) value , the 5 a (ty pical) internal soft start current (i ss ) begin s charging the soft start c apacitor (c ss ) , causing the voltage on the ss pin (v ss ) to rise. while v ss is less than 0.5 2 v (typical) , the ADP1972 swit ching control remains disabled. when v ss reaches 0.5 2 v (typical) , switching is enabled , and regulation of the ADP1972 control loop begins. as c ss continues to charge and v ss rises, the pwm duty cycle gradually increases , allowing the output voltage to rise linearly with litt le to no over - shoot during startup. c ss charges and v ss rises until v ss reaches the internal vreg voltage (5 v typical). when the internal system duty cycle is less than the soft start duty cycle, t he internal control loop take s control of the ADP1972 . see figure 18 for a soft start diagram . there is an active, internal, pull - down resistor on the ss pin that discharges c ss when the device shut s down to prevent a fault from occurring. vreg vout 0.52v 0v v ss enable ADP1972 begin regulation t reg 1 1884-022 figure 18 . soft start diagram operating modes the ADP1972 c an be programmed to operate as an asynchronous boost or as an asynchronous buck. if th e mode pin is driven low by less than 1.05 v (typical), then the ADP1972 operate s in a boost configuration. a b oost configuration is ideal for power recycling and discharging in battery charging ap plications. w hen the mode pin is driven high by greater than 1. 2 0 v (typical), the ADP1972 operate s in a buck configuration for battery charging. see figure 19 and figure 20 for the ADP1972 behavior in each mode . when the ADP1972 is enabled, the internal ld o regulator connected to the vreg pin also powers up. on the rising edge of vreg, the state of the mode pin is latched , preventing the mode of operation f rom being changed while the device is enabled. to change between boo st and buck modes of operation, sh utdown or disable the ADP1972 , adjust the mode pin to change the operating mode , and restart the system. the operating mode can b e changed when the en pin is driven low, the fault pin is driven low , or the ADP1972 is disabled via a tsd event or uvlo condition . on the rising edge of the fault control signal, the state of the mode pin is latched , preventing the mode of operation from being changed while the device is enabled. 0.5v 4.5v boost mode configuration mode 1.05v (typical) v scfg 4.53v (typical) comp 0v dh dl 0v internal ramp (4v p-p) vreg (5v typical) vreg (5v typical) 0v 1 1884-023 figure 19 . signal diagram for boost configuration 0.5v 4.5v buck mode configuration mode 1.2v (typical) v scfg 4.53v (typical) comp 0v dh dl 0v internal ramp (4v p-p) vreg (5v typical) vreg (5v typical) 0v 1 1884-024 figure 20 . signal diagram for buck configuration rev. 0 | page 11 of 20 free datasheet http://www..net/
ADP1972 data sheet pwm drive signals the ADP1972 has two output drive signals, dh and dl, that are compatible with drivers similar to the ir2110s. the drive signal dl is active when the mode pin is logic low and the ADP1972 is c onfigured in the boost/ recycle mode. the dl drive signal turn s on and off the low - side switch driven from the external driver. while in the boost/ recycle mode, the dh signal is driven low to prevent the high - side switch from turning on and only allow s the body diode to conduct. the drive signal dh is active when the mode pin is logic high and the ADP1972 is configured in the buck/charg e mode. the dh drive signal turn s on and off the high - side switch driven from the external driver. while in the buck/charge mode, the dl signal is driven low to prevent the low - side switch from turning on , and it only allow s the body diode to conduct. when driving capacitive loads with the dh and dl pins, a 20 ? resisto r must be placed in series with the capacitive load to reduce ground noise and ensure signal integrity. external c omp control the ADP1972 comp pin is the input to the error amplifier that controls the pwm output on the dh pin or dl pin. the ADP1972 u ses voltage mode control that compares an error signal , applied to the comp pin by a n external device , such as the ad8450 , to an internal 4 v p - p triangle waveform. as the load changes, the error signal increase s or decrease s. t he internal pwm comparator determine s the appropriate duty cycle drive signal by monitoring the error signal at the comp pin and the internal 4 v p - p ramp signal. the internal pwm comparator subsequently drive s the external gate driver at the determi ned duty cycle through the dh and dl drive control pins . the functional voltage range of the comp pin is from 0 v t o 5 .0 v. i f v comp is less than 0.5 v ( typical ) , the dh a nd dl outputs are disable d . if v comp is between 0.5 v and 4.5 v , the ADP1972 regulate s the dh and dl outputs accordingly. if v comp is greater than 4.5 v, the ADP1972 operate s the dh and dl outputs at the maximum pro grammed duty cycle (98% default ) . the input to the comp pin must never exceed the 5.5 v absolute maximum rating. the dl and dh s ignals swing from vreg (5 v typical) to ground . the external fet driver used must have input control pins compatible with a 5 v logic signal. current limit the ADP1972 features a peak hiccup curren t limit implementation. when the peak inductor current exceeds the programmed current limit for more than 500 consecutive clock cycles, 5 .2 ms (typical) for a 100 khz programmed frequency, the peak hiccup c urrent limit condition occurs. pwm regu lation of t he output voltage then disables for 500 clock cycles, which is enough time for the output to discharge , and the average power dissipation to reduce. when the 500 clock cycles have expired, the adp19 72 restart s . when the ss pin exceeds 0.5 2 v (typical), the ADP1972 resume s pwm regulation. figure 21 shows the current limit block diagram for peak curre nt limit protection. vreg r s cl 500mv 300mv i cl 20a r cl 20k m2 mode select 1 1884-025 figure 21 . current limit block diagram pwm frequency contro l the freq, sync, and scfg pins are all used to determine the source, frequency, and synchronization of the clock signal that operates the pwm contr ol of the ADP1972 . internal frequency control the ADP1972 frequency can be programmed with an external resistor connected between freq and ground. the range of frequency can be set from a minimum of 50 khz to a maximum of 300 khz. if the scfg pin is tied to vreg , forcing v scfg 4.5 3 v , or if the scfg pin is left floating, the sync pin is configured as an output , and the ADP1972 operate s at the frequency set by r freq , which output s from the sync pin through the open drain device. the output clock of the sync pin operates with a 50% (typical) duty cycle. in this configuration, the sync pin can be used to synchronize other switching regulators in the system to the ADP1972 . when the sync pin is configured as an output, a n external pull - up resistor is needed from the sync pin to an external supply. the vreg pin of the ADP1972 is used as the external supply rail for the pull - up resistor. external frequency control when v scfg 0.5 v, the sync pin is configured as an input , an d the ADP1972 synchronize s to the external clock applied to the sync pin and operates as a slave device . this synchronization allows the ad p1972 to operate at the same switchin g frequency with the same phase as other switching regulators or devices in the system . when operating the ADP1972 with an external clock, select r freq to prov ide a frequency that approximates but is no t equal to the external clock frequency , which is further explained in the applications information section . operating frequency phase shift when the voltage applied to the scfg pin is 0. 6 5 v < v scfg < 4. 2 5 v, the sync pin is configured as an input , and the ADP1972 synchronize s to a phase shifted version of the external clock applied to the sync pin. to a dju st the phase shift, plac e a resistor (r scfg ) from scf g to ground . the phase shift reduces the input supply ripple for systems containing mul tiple switching power supplies. rev. 0 | page 12 of 20 free datasheet http://www..net/
data sheet ADP1972 maximum duty cycle the maximum duty cycle of the a dp1972 can be externally programmed to any value between 0% and 98% via an external resistor on the dmax pin connected from dmax to ground. t he maximum duty cycle default s to 98% if dmax is left floating, is tied to vreg, or is programmed to a value great er than 98%. external f ault signaling the ADP1972 is equipp ed with a fault pin that signal s the ADP1972 when an external fault condition o ccurs. the external fault signal stops pwm operation of the system to avoid damage to the application and components. when a voltage less than 1.05 v (typical) is applied to the fault pin, the adp19 72 disables . in this state, the dl and dh pwm drive signals are both driven low to prevent switching of the system dc - to - dc conv erter , and the soft start is reset. when a voltage greater than 1.20 v (typical) is applied to the fault pin, the ADP1972 begin s switching. a voltage ranging from 0 v to 60 v can be applied to the fault pin of the ADP1972 . thermal shutdown (tsd) the ADP1972 has a tsd protection ci rcuit. the thermal shutdown trigger s and disable s switching when the junction temperature of the ADP1972 reaches 150c (t ypical). while in tsd, the dl and dh signals are driven low and the c ss capacitor discharges to ground . vreg remain s high. when the junction temperature decreases to 135c (typical), the ADP1972 re start s the application control loop. rev. 0 | page 13 of 20 free datasheet http://www..net/
ADP1972 data sheet applications informa tion the ADP1972 has many programmable features that are optimized and controlled for a given application. the ADP1972 provides pins for selecting the operating mode, controlling the current limit, selecting an internal or external clock, setting the operating frequency, phase shifting the operating frequency, programming the maximu m duty cycle, and adjusting the soft start. buck or boost selection to operate the ADP1972 in boost /recycle mode, apply a voltage less than 1.05 v (typical) to the mode pin. to operate the ADP1972 in buck /discharge mode, drive the mode pin high, greater than 1.2 v (typical). the state of the mode pin can only be changed when the adp19 72 is shutdown via the en pin , or disabled via a n external fault condition signaled on the fault pin , a tsd event, or a uvlo condition. selecting r s to set the current l imit see figure 21 for the current - limit blo ck diagram for peak cur rent - limit control . use using the following equation to set the current limit : ( ) s pk r i mv 100 ma = i pk is the desired peak current - limit in ma . r s is the sense resistor used to set the peak current limit in ? . when the ADP1972 is configured to operate in buck/ch arge mode, the internal current - limit reference is set to 300 mv (typical) . w hen the ADP1972 is configured to operate in boost/ recycle mode, the internal current - limit reference is set to 500 mv (typical) . the external resistor, r cl , is needed to offset the current properly to detect the peak in both buck and boost operation. set t he val ue of r cl to 20 k?. in operation, the equation fo r setting the peak current follows: for buck/charge mode, it is v ref ( buck ) = (i cl ) ( r cl ) ? ( i pk ) ( r s ) (2 ) for boost/ recycle mode, it is v ref ( boost ) = (i cl ) (r cl ) + ( i pk ) ( r s ) (3 ) where : v ref (buck) = 300 mv , typical. v ref (boost) = 500 mv , typical. i cl = 20 a , typical . r cl = 20 k?. the ADP1972 is designed so that the peak current limit is the same in both the buck mode and boost mode of operation. a 1% or better tolerance for the r cl and r s resistors is recommended . adjusting the operat ing frequency if the scfg pin is tied to vreg , forcing v scfg 4.5 3 v , or if scfg is left floating and internally tied to vreg , the ADP1972 operates at the frequency set by r freq , and the sync pin outputs a clock at the programm ed frequency. w hen v scfg 4.5 3 v , the output clock on the sync pin can be used as a master clock in applications that require synchr onization. if v scfg is 0.5 v, the sync pin is configured a s an input , and the ADP1972 operates as a slave device. as a slave device, the ADP1972 synchronizes to the external clock applied to the sync pin. if the voltage applied to the scfg pin is 0. 6 5 v < v scfg < 4. 2 5 v , and a resistor is connected between scfg and ground , the sync pin is configured as an input , and the ADP1972 synchronize s to a phase shifted version of the external clock applied to the sync pin . whether o perating the ADP1972 as a master or as a slav e device , r freq must be carefully selected using the equations in the following sections . selecting r freq for a master device when v scfg is 4 .5 3 v, t h e ADP1972 operates as a master device . when functioni ng as a master device, the ADP1972 operates at the frequency set by the external r freq resistor connected between freq and ground , and the ADP1972 output s a clock at the program m ed frequency on the sync pin. figure 22 shows the relationship between the programmed switching frequency (f set ) and the value of r freq . 210 30 50 70 90 110 130 150 170 190 50 100 150 200 250 300 r freq (master) n f set (khz) 1 1884-026 figure 22 . r freq vs. switching frequency (f set ) use the following equation t o calculate the r freq value for a de sired master clock synchronization frequency : ( ) set master freq f r = f set is the switching frequency in khz. r freq ( master ) is the resistor in k to set the frequency for master devices. rev. 0 | page 14 of 20 free datasheet http://www..net/
data sheet ADP1972 selecting r freq for a slave device to configure the ADP1972 as a slave device, drive v scfg < 4.5 3 v. when functioning as a slave device , the ADP1972 operate s at the frequency of the external clock applied to the sync pin. to ensure proper synchronization, select r freq to set the frequency to a value slightly slower than that of the master clock by using the following equation: r freq ( slave ) = 1.11 r freq ( master ) (5 ) w here : r freq ( master ) is the resistor value that corresponds to the frequency of the maste r clock applied to the sync pin. r freq ( s l av e ) is the resistor value that appropriately scales the frequency for the slave device, and 1.11 is the r freq slave to master ratio for s ynchronization. the frequency of the slave device is set to a frequency slightly lower than that of the master device to allow the digital synchronization loop of the ADP1972 to synchronize to the master clock period. the slave device has approximately a 30% range capability to adjust to match the master clock value. setting r freq ( sl av e ) to 1.11 larger than r freq (master) run s the synchronization loop in approximately the center of the adjustment range. programming the external clock phase shift if a phase shift is not required for slave devices, connect scfg of each slave device to ground. for devices that requir e a phase shifted version of the synchronization clock that is applied to the sync pin of the slave devices , connect a resistor ( r scfg ) from scfg to ground to program the desired phase shift. to determine the r scfg for a desired phase shift ( shift ) , start by calculating the frequency of the slave clock (f slave ). ) freq(slave slave r f 4 10 (khz) = ( ) ? = slave slave f t ( ) here t s l av e is the period of the master clock in s . f s l av e is the frequency o f the master clock in khz . next , determine the phase time delay ( t delay ) for the desired phase shift ( shift ) using the following equation : ( ) ( ) slave shift delay t t = t del ay is the phase delay in s . shift is the desired phase shift. lastly , t o calculate the phase delay ( t delay ), use the following equation: r scfg (k?) = 0.45 r freq ( slave ) (k?) + 5 0 10 6 t delay (s) (9 ) w here : r scfg is th e corresponding resistor for the desired phase shift in khz . when using the phase shift feature, connec t a capacitor of 47 pf or greater in parallel with r scfg . alternatively, the scfg pin can be controlled with a voltage source. when using an independent voltage source, ensure v scfg vreg under all conditions. when the ADP1972 is disabled via the en pin or uvlo, vreg = 0 v , and the voltage source must adjust accordingly to ensure v scfg vreg. figure 23 shows the internal voltage ramp of the ADP1972 . th e voltage ramp has a well controlled 4 v p - p . 4.5v t 0.5v 0.01t 0.99t 1 1884-027 figure 23 . internal voltage ramp programming the maximum duty cycle the ADP1972 is designed with a 98% (typical) internal maximum duty cycle. by connecting a resistor from dmax to ground , the maximum duty cycle can be programmed at any value from 0% to 98%, using the following equation: ( ) ? = freq dmax freq max r r v d ( ) here d max is the programmed maximum duty cycle. r dmax is the value of the resistance used to program the maximum duty cycle . the current source of dmax is equivalent to the programmed current of the freq pin: freq freq freq dmax r v i i = = i dmax = i freq = t he current programmed on the freq pin. the maximum allowable duty cycle of the ADP1972 is 98% (typical). if the resistor on dmax sets a maximum duty cycle larger than 98%, the ADP1972 default s to its internal maximum. if the 98% internal maximum duty cycle is sufficient for the application, tie the dmax pin to vreg or leave it floating. the c dmax capacitor connected from the dmax pin to gnd must be 47 pf or greater. rev. 0 | page 15 of 20 free datasheet http://www..net/
ADP1972 data sheet adjusting the soft start period the ADP1972 has a programmable soft start feature that prevents output voltage overshoot during startup. refer to figure 18 for a soft start diagram. use the following equation to calculate the delay time before switching is enabled (t reg ): ss ss reg c i t = 0.52 (1 2 ) where i ss = 5 a , t ypical. a c ss c apacitor is not required for the ADP1972 . when the c ss capacitor is not used, the internal 5 a (typical) current source immediately pull s the ss pin voltage to vreg . when a c ss capacitor i s not used, there is no soft star t control internal to the ADP1972 , and the system c ould produce a large output overshoot and a large peak inductor s pike during startup . when a c ss is not used, e nsure that the output overshoot is not large enough to trip the hiccup current limit during startup . rev. 0 | page 16 of 20 free datasheet http://www..net/
data sheet ADP1972 pcb layout guideline s for high efficiency, good regulation, and stability, a well designed pcb layout is required. use the following guidelines when designing the pcb ( see figure 16 for the block diagram and figure 2 for the pin configuration). ? keep the low effective series resistance ( esr ) input supply capacitor for vin (c in ) as close as po ssible to the v in and gnd pins to minimi ze noise being i n jected into the device from board parasitic inductance. ? keep the low esr input supply capacitor for vreg (c vreg ) as close as possible to the vreg and gnd pins to minimize noise being i n jected into the device from b oard parasitic inductance. ? place the components for the scfg, freq, dmax, and ss pins close to the corresponding pins . tie t hese components collectively to an agnd plane that makes a k elvin connection to the gnd pin. ? keep the trace from the comp pi n to the accompanying device (for example, ad8450 ) as short as possible. avoid routing this trace near switching signals and shield the trace if possible. ? place any trace or components for the sync pin away f rom sensitive analog nodes. when using an external pull - up, i t is best to use a local 0.1 f bypass capacitor from the supply of the pull - up resistor to gnd. ? keep the traces from the dh and dl pins to the external components as short as possible to minimiz e parasitic inductance and capacitance , which affect the control signal. the dh and dl pins are switching nodes ; do not route them near any sensitive analog circuitry. ? keep high current traces as short and as wide as possible. ? connect t he ground connectio n of the ADP1972 directly to the ground connection of the current sense , r s , resistor. ? connect cl through a 20 k? resistor directly to r s . ? use a k elvin connection shown in figure 24 and figure 25 from the following : o t he gnd pin to the ground point f or r s o t he gnd sense pin to the ground point for r s o t he system power ground to the ground point of r s extra re sistance due to pcb routing introduce s a voltage difference between the gnd pin and the gnd sense pin . this voltage difference must not exceed 0.3 v. ? when building a system with a master and multiple slave devices, the capacitance of the trace attached to the sync p in must be minimized. o for small systems with only a few slave device s, a resistor connected in series between the master sync signal and the slave sync input pins limit s the capacitance of the trace and reduce s the fast ground currents that can inject nois e into the master device. o for larger applications, the series resistance is not enough to isolate the master sync clock. in large r systems, use an external buffer to reduce the capacitance of the trace. the external buffer has the drive capability to suppo rt a large number of slave devices. r s gnd sense gnd cl r cl n nmos power fet source ground bus 1 1884-028 figure 24 . recommended r s kelvin ground c onnection cl gnd sense gnd 1 1884-029 figure 25 . recommended r s kelvin ground c onnection on pcb layout rev. 0 | page 17 of 20 free datasheet http://www..net/
ADP1972 data sheet outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 26 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option order ing quantity ADP1972aruz - r7 ?40c to +125c 16- lead thin shrink small outline package [tssop] , 13 tape and reel ru -16 1,000 ADP1972aruz - rl ?40c to +125c 16- lead thin shrink small outline package [tssop], 7 tape and reel ru -16 2,500 ADP1972 - evalz evaluation board 1 z = rohs compliant part . rev. 0 | page 18 of 20 free datasheet http://www..net/
data sheet ADP1972 notes rev. 0 | page 19 of 20 free datasheet http://www..net/
ADP1972 data sheet no tes ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11884 - 0 - 1/14(0) rev. 0 | page 20 of 20 free datasheet http://www..net/

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